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Micrel, Inc.
Pin Description: Signal Descriptions by Group (Continued)
KSZ9692PB, KSZ9692PB-S
Pin Number
T2, U1, L5,
N4, P3, R2,
T1, M4, K5,
N3, P2, R1,
L4, M3, P1,
K4
L3
Pin Name
SDATA[15..0]
ECS2
Pin Type
Ipu/O
O
Pin Description
SRAM DATA Bus.
Bidirectional Bus for 16-bit DATA In and DATA Out. The KSZ9692PB,
KSZ9692PB-S also supports 8-bit data bus for ROM/SRAM/FLASH/EXTIO
cycles.
This data bus is shared between NAND, ROM/SRAM/FLASH/EXTIO devices.
External I/O Chip Select 2, asserted Low.
Three External I/O banks are provided for external memory-mapped I/O
operations. Each I/O bank stores up to 16Kbytes. ECSN signals indicate which
of the three I/O banks is selected.
N1
ECS1
O
External I/O Chip Select 1, asserted Low.
Three External I/O banks are provided for external memory-mapped I/O
operations. Each I/O bank stores up to 16Kbytes. ECSN signals indicate which
of the three I/O banks is selected.
M2
ECS0
O
External I/O Chip Select 0, asserted Low.
Three External I/O banks are provided for external memory-mapped I/O
operations. Each I/O bank stores up to 16Kbytes. ECSN signals indicate which
of the three I/O banks is selected.
K3
RCSN1
O
ROM/SRAM/FLASH(NOR) Chip select 1, asserted Low.
The KSZ9692PB, KSZ9692PB-S can access up to two external
ROM/SRAM/FLASH memory banks. The RCSN pins can be controlled to map
the CPU addresses into physical memory banks.
L1
RCSN0
O
ROM/SRAM/FLASH(NOR) Chip select 0, asserted Low.
The KSZ9692PB, KSZ9692PB-S can access up to two external
ROM/SRAM/FLASH memory banks. The RCSN pins can be controlled to map
the CPU addresses into physical memory banks.
This bank is configurable as boot option
N2
EWAITN
I
External Wait asserted Low.
This signal is asserted when an external I/O device or
ROM/SRAM/FLASH(NOR) bank needs more access cycles than those defined
in the corresponding control register.
M1
EROEN
(WRSTPLS)
Ipd/O
ROM/SRAM/FLASH(NOR) and EXTIO Output Enable, asserted Low.
When asserted, this signal controls the output enable port of the specified
ROM/SRAM/FLASH memory and EXTIO device.
J5
ERWEN1
O
ROM/SRAM/FLASH(NOR) and EXTIO Write Byte Enable, asserted Low.
When asserted, this signal controls the byte write enable of the memory device
SDATA[15..8] for ROM/SRAM/FLASH and EXTIO access.
J4
ERWEN0
Ipd/O
ROM/SRAM/FLASH(NOR) and EXTIO Write Byte Enable, asserted Low.
When asserted, this signal controls the byte write enable of the memory device
SDATA[7..0 or 15..0] for ROM/SRAM/FLASH and EXTIO access.
May 2011
11
M9999-051111-4.0
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